`timescale 1ns / 1ps

module TLV5618_Driver_tb();

	reg				clk		;
	reg				rst_n		;
	reg	[15:0]	DAC_data	;
	reg				set_go	;
	wire				set_done	;
	wire				DAC_cs_n	;
	wire				DAC_sclk	;
	wire				DAC_din	;

	TLV5618_Driver TLV5618_Driver(
		.clk			(clk		),
		.rst_n		(rst_n	),
		.DAC_data	(DAC_data),
		.set_go		(set_go	),
		.set_done	(set_done),
		.DAC_cs_n	(DAC_cs_n),
		.DAC_sclk	(DAC_sclk),
		.DAC_din		(DAC_din	)
	);

	initial clk = 1;
	always#10 clk = ~clk;
	
	initial begin
		rst_n = 0;
		set_go = 0;
		DAC_data = 0;
		#201;
		rst_n = 1;
		#200;
		
		DAC_data = 16'hC_AAA; // 16'b1100_1010_1010_1010
		set_go = 1;
		#20;
		set_go = 0;
		#200;
		wait(set_done);
		#20001;
		
		DAC_data = 16'h4_555; // 16'b0100_0101_0101_0101
		set_go = 1;
		#20;
		set_go = 0;
		#200;
		wait(set_done);
		#20001;	
		
		DAC_data = 16'h1_555; // 16'b0001_0101_0101_0101
		set_go = 1;
		#20;
		set_go = 0;
		#200;
		wait(set_done);
		#20001;

		DAC_data = 16'hf_555; // 16'b1111_0101_0101_0101
		set_go = 1;
		#20;
		set_go = 0;
		#200;
		wait(set_done);		
		#20001;		
		$stop;
	end
endmodule
